1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacturing a semiconductor device, and particularly to a semiconductor device having an electrode made of a stacked structure of metal/(poly)silicon and a manufacturing method thereof.
2. Description of the Background Art
FIG. 30 shows a longitudinal section of an MOS transistor 101P as a semiconductor device according to a first conventional technique, which has a polycide gate composed of a stacked structure of silicide/polysilicon. The MOS transistor 101P may be called xe2x80x9ca DRAM transistorxe2x80x9d since it is used as a transistor in the memory cell area in a DRAM (Dynamic Random Access Memory).
As shown in FIG. 30, the silicon substrate 1P is sectioned by trench isolations 2P into areas in which MOS transistors are formed. A gate insulating film 3P is formed on the main surface of the silicon substrate 1P, which is made of a film of silicon oxide obtained by applying thermal oxidation to the main surface.
A gate electrode GE1P is formed on the gate insulating film 3P, which is comprised of a polysilicon layer 4P and a silicide layer 60P stacked in this order as the main materials. Silicon oxide films or reoxidation films 14P are formed on the sides of the polysilicon layer 4P.
This polycide gate structure is formed as described below. First, polysilicon and silicide are sequentially stacked and a TEOS oxide film (not shown) is formed thereon. The TEOS oxide film is then patterned by photolithography and the silicide layer and the polysilicon layer are etched together by using the patterned TEOS oxide film as a hard mask in anisotropic etching. Subsequently, reoxidation (thermal oxidation) is applied to the sides of the etched polysilicon layer. The gate electrode GE1P composed of the polysilicon layer 4P, the reoxidation films 14P, and the silicide layer 60P is thus formed as shown in FIG. 30.
Side wall spacers or spacers 7P are formed in contact with the gate insulating film 3P and the sides of the polysilicon layer 4P and the silicide 60P. The spacers 7P are formed by forming a dielectric film, such as a TEOS oxide film or silicon nitride film, to cover the gate electrode GE1P and then etching it back.
The structure also has source/drain extension regions 6P and source/drain regions 8P (hereinafter these are also referred to as xe2x80x9csource/drain regions 9Pxe2x80x9d together) formed in the main surface of the silicon substrate 1P. These regions 6P and 8P are formed by ion implantation.
Although not shown in FIG. 30, interlayer film is formed to cover the gate electrode GE1P and interconnections connected to the gate electrode GE1P and the like are formed on the interlayer film.
Next, FIG. 31 shows a longitudinal section of an MOS transistor 102P as a semiconductor device according to a second conventional technique. The MOS transistor 102P may be referred to as xe2x80x9ca logic transistorxe2x80x9d since it is applied to a logic circuit, for example.
As shown in FIG. 31, the MOS transistor 102P has a gate electrode GE2P and salicide layers or silicide layers 10P as source/drain region electrodes, both of so-called salicide structure formed by self-aligned silicidation. The structure is equivalent to that of the above-described MOS transistor 101P (see FIG. 30) in other respects. The MOS transistor 102P is manufactured by the following method.
First, the main surface of the silicon substrate 1P is thermally oxidized to form a silicon oxide film (which forms the gate insulating film 3P later). Then a polysilicon layer and a TEOS oxide film are stacked on the exposed surface of the silicon oxide film and the TEOS oxide film is patterned by photolithography. Subsequently, the polysilicon layer is etched by using the patterned TEOS oxide film as a hard mask in anisotropic etching. Next, the source/drain extension regions 6P are formed by ion implantation and then reoxidation is applied to the sides of the etched polysilicon layer to form reoxidation films 14P. The spacers 7P are then formed and the source/drain regions 8P are formed by ion implantation.
Subsequently, the TEOS oxide film used as a hard mask is etched to expose the upper surface of the polysilicon layer. Next, a metal film, such as cobalt (Co), is formed entirely over the silicon substrate 1P and it is annealed. This annealing causes silicidation (salicidation) of the metal film and the upper surface of the polysilicon layer and the exposed surface of the silicon substrate 1P, which forms the silicide layers or salicide layers 70P and 10P. Next the unreacted metal film is removed by etching. Thus the gate electrode GE2P composed of the silicide layer 70P, the polysilicon layer 4P, and the reoxidation films 14P is formed as shown in FIG. 31.
Next, FIG. 32 shows a longitudinal section of a semiconductor device (which may be referred to as a hybrid transistor) 104P as a semiconductor device according to a third conventional technique, which has the MOS transistor 101P and an MOS transistor 103P corresponding to the MOS transistor 102P. While the MOS transistor 103P is the same as the above-described MOS transistor (logic transistor) 102P in that it is applied to a logic circuit, for example, it differs from the MOS transistor 102P in that the gate electrode GE1P of the MOS transistor (DRAM transistor) 101P is applied to its gate electrode. A method for manufacturing the hybrid transistor 104P will now be described.
As shown in FIG. 32, the regions for formation of the MOS transistors 101P and 103P are sectioned by the trench isolations 2P. The region in which the DRAM transistor 101P is formed is referred to as a memory cell area and the region in which the logic transistor 103P is formed is referred to as a logic area.
Subsequently, thermal oxidation is applied to the main surface of the silicon substrate 1P to form a silicon oxide film which forms the gate insulating film 3P later. Next, the memory cell area is covered with a resist mask by photolithography, and the silicon oxide film in the logic area is removed by wet etching. Then, the resist mask is removed, and thermal oxidation is performed again to form a thin silicon oxide film in the logic area and a thick silicon oxide film in the memory cell area. After that, the gate electrodes GE1P are formed in the two MOS transistors 101P and 103P, as described in the method for manufacturing the MOS transistor 101P. In the following manufacturing steps, basically, given manufacturing process step is applied to one of the memory cell area and the logic area with the other covered by resist mask or the like. For example, in the process steps for forming the source/drain regions 9P in the MOS transistors 101P and 103P, ion implantation is applied sequentially to the memory cell area and the logic area. Then, with a mask formed on it except in the vicinities of the source/drain regions 9P in the logic area, a metal film, e.g. cobalt (Co), is deposited on the entirety of the silicon substrate 1P. The salicide layers 10P are then formed by annealing on the source/drain regions 8P (or 9P) in the logic area. Unreacted metal film is then etched away.
The MOS transistors 101P to 104P according to the conventional techniques have the following problems (1) to (5).
 less than Problem (1): Problems due to Resistance of Silicide Layer greater than 
The polycide gate electrodes GEIP and GE2P of the conventional MOS transistors 101P to 104P have higher gate resistance than a gate electrode composed of a stacked structure of polysilicon layer/metal layer (hereinafter referred to as a polymetal gate (electrode)). The conventional MOS transistors 101P to 104P therefore have problems of large interconnection delay, generating much heat, etc.
 less than Problem (2): Problem in Formation of Gate electrode greater than 
The gate electrodes GE1P and GE2P of the conventional MOS transistors 101P to 104P are difficult to form, since they have larger aspect ratio than the polymetal gate. More specifically, the conventional MOS transistors 101P to 104P have high gate resistivity as stated above, and therefore the silicide layers 60P and 70P having high resistivity are formed thick to reduce the resistance of the gate electrodes GE1P and GE2P. For example, while a sheet resistance of 2 xcexa9/sqr can be obtained with tungsten (W) having a thickness of 60 nm, realizing it with tungsten silicide (WSi) requires a film thickness of 400 nm, and realizing it with cobalt silicide (CoSi) requires a film thickness of 130 nm. In these cases, in the gate electrode formation process, anisotropic etching must be applied to a film having a thickness of about 300 to 600 nm, i.e. the thickness of the silicide layer plus the thickness of the polysilicon layer (about 100 to 200 nm) and the hard mask (about 50 to 100 nm). Under such a condition, it is very difficult to form a gate electrode having a gate length of 0.2 xcexcm or smaller at high yield.
 less than Problem (3): Problem in Ion Implantation Process greater than 
In relation to the problem (2) above, a problem is encountered in the ion implantation in the process of forming the source/drain regions 9P. That is to say, a large implant angle cannot be set in the ion implantation since the aspect ratio of the gate electrode is high as stated above, and therefore ions must be implanted almost vertically. In this case, the implant angle must be set small in oblique implantation such as pocket implantation (also called halo implantation, NUDC, etc.), for example, which causes inconveniences in the characteristics of the MOS transistor, such as reduction in the short-channel characteristic.
 less than Problem (4): Problem due to Salicide Structure greater than 
In the MOS transistor 102P having the salicide structure, the two salicide layers 10P and 70P have equivalent film thickness. Accordingly, when the silicide layer 70P included in the gate electrode GE2P is formed thick to reduce the sheet resistance of the gate electrode, the salicide layers 10P on the source/drain regions 8P are formed thick, too. When the salicide layers 10P are formed deeper than the junction between the source/drain regions 9P and the silicon substrate 1P, the leakage current increases at the junction. Such junction leakage current may be suppressed or prevented by forming the source/drain regions 9P further deeper. However, forming the source/drain regions 9P still deeper raises another problem that the short channel-characteristic of the MOS transistor is reduced.
As stated above, the MOS transistor 102P manufactured by the salicide process has the problem that setting of the thickness of the salicide layers 10P and 70P is very difficult.
 less than Problem (5): Problem Caused When Metal Layer is Substituted for Silicide Layer of Gate Electrode greater than 
To solve the problems (1) to (4), a polymetal gate can be used in place of the polycide gate. However, simply replacing the silicide layer with the metal layer raises the following problems.
First, when the reoxidation film is formed by thermal oxidation after forming and patterning the polysilicon layer and the metal layer, and also when oxide film like the spacers 7P and interlayer film are formed, the metal layer is exposed to the oxidation atmosphere and oxidized (from the exposed surface). Also, the metal layer will be oxidized when thermal process is performed with oxide film like the spacers 7P in contact with the metal layer. Then the original object of reducing the resistance of the gate electrode cannot be achieved.
(1) According to a first aspect of the present invention, a semiconductor device comprises: a silicon layer; a silicon-containing layer which is located on a side wall of the silicon layer; a metal layer in contact with a main surface of the silicon layer; and a protective layer provided on a side wall of the metal layer and having a side wall smoothly connected to a side wall of the silicon-containing layer on the opposite side to the silicon layer, and in the semiconductor device of the first aspect, the silicon layer, the silicon-containing layer, the metal layer and the protective layer constitutes a conductive layer.
(2) Preferably, according to a second aspect, in the semiconductor device, the side wall of the protective layer does not overhang relative to the side wall of the silicon-containing layer.
(3) Preferably, according to a third aspect, in the semiconductor device, the protective layer is made of a silicide.
(4) Preferably, according to a fourth aspect, in the semiconductor device, the protective layer is made of a dielectric which does not contain oxygen.
(5) Preferably, according to a fifth aspect, in the semiconductor device, the dielectric which does not contain oxygen is silicon nitride.
(6) Preferably, according to a sixth aspect, in the semiconductor device, the silicon-containing layer is out of contact with the metal layer.
(7) Preferably, according to a seventh aspect, in the semiconductor device, the metal layer at least comprises a barrier metal layer in contact with the silicon layer.
(8) Preferably, according to an eighth aspect, in the semiconductor device, the conductive layer forms a gate electrode of an MIS transistor.
(9) According to a ninth aspect of the present invention, a semiconductor device manufacturing method comprises the steps of: (a) forming a first silicon layer; (b) forming a metal layer in a given region on a main surface of the first silicon layer; (c) forming a protective layer on a side wall of the metal layer; and (d) after the step (c), removing part of the first silicon layer which is not covered by the protective layer and the metal layer.
(10) Preferably, according to a tenth aspect, in the semiconductor device manufacturing method, the step (c) comprises the steps of; (c-1) forming a second silicon layer on the side wall of the metal layer at least, and (c-2) causing silicidation reaction to occur between the metal layer and the second silicon layer to form a silicide layer as the protective layer.
(11) Preferably, according to an eleventh aspect, the semiconductor device manufacturing method further comprises a step (f) of applying an isotropic etching to the metal layer before the step (c).
(12) Preferably, according to a twelfth aspect, in the semiconductor device manufacturing method, the step (c) comprises the steps of; (c-1) forming a dielectric layer not containing oxygen to cover the metal layer in contact with the side wall of the metal layer, and (c-2) etching back the dielectric layer, leaving the dielectric layer as the protective layer on the side wall of the metal layer at least.
(13) Preferably, according to a thirteenth aspect, the semiconductor device manufacturing method further comprises, after the step (d), a step (g) of oxidizing a side wall of the silicon layer to form a silicon oxide film.
(14) Preferably, according to a fourteenth aspect, in the semiconductor device manufacturing method, the oxidation in the step (g) is performed in such a manner that the silicon oxide film is out of contact with the metal layer.
(15) Preferably, according to a fifteenth aspect, in the semiconductor device manufacturing method, the step (b) at least comprises a step of forming a barrier metal layer in contact with the silicon layer.
(16) A sixteenth aspect of the present invention is related to a semiconductor device which is manufactured by the above-described semiconductor device manufacturing method.
(1) According to the first aspect of the invention, both side walls of the protective layer and the silicon-containing layer are smoothly connected, so that voids are not formed when another layer (e.g. the side wall spacer in an MIS transistor) is formed on the side walls. This prevents the problem that oxygen or chemicals used in cleaning treatments enter through breaks (peels) in the layer or pinholes formed by such voids to oxidize or/and dissolve or deteriorate the metal layer. As a result, it is possible to certainly prevent oxidation of the metal layer and prevent an increase in resistance of the conductive layer.
As compared with a conventional conductive layer composed of a silicon layer and a silicide layer, the conductive layer made of a silicon layer and a metal layer as the base materials provides the following effects. That is to say, when the thickness of the metal layer is set equal to that of the silicide layer, the resistance of the conductive layer can be much lower than that of the conventional conductive layer. This reduces the amount of heat generated by the semiconductor device and reduces the interconnection delay to realize higher speed operation. When the resistance value of the metal layer is set equal to that of the silicide layer, the thickness of the conductive layer can be much smaller than that of the conventional conductive layer. In this case, when the conductive layer is applied as a gate electrode in an MIS transistor, for example, the aspect ratio of the gate electrode can be smaller than that in the conventional conductive layer, so that the ion implantation in the step of forming the source/drain region can be carried out reliably. This provides an MIS transistor with improved short-channel characteristic. Further, reducing the thickness of the conductive layer remarkably facilitates improvement of the flatness of interlayer film and the like which are formed on the conductive layer, which allows the semiconductor device to be formed in an increased number of layers.
(2) According to the second aspect, the effect of preventing formation of voids mentioned in the first aspect can be more certainly obtained since the side wall of the protective layer does not overhang relative to the side wall of the silicon-containing layer. This more certainly prevents oxidation of the metal layer and therefore prevents the increase in the resistance.
(3) According to the third aspect, the protective layer can be formed in a self-aligned manner by forming the metal layer and then depositing silicon on the side wall of the metal layer and annealing it, for example. Thus the protective layer can be formed simply and reliably.
(4) According to the fourth aspect, the metal layer is not oxidized due to the composition of the dielectric layer since the protective layer does not contain oxygen. Thus the effect of preventing oxidation is effectively exerted and the increase in resistance of the metal layer can be prevented more reliably.
(5) According to the fifth aspect, silicon nitride is used as the protective layer (the dielectric not containing oxygen), so that the oxidation resistance and chemical resistance can be improved as compared with an application in which silicide is used as the protective layer.
(6) According to the sixth aspect, the silicon-containing layer is out of contact with the metal layer. Accordingly the effect of preventing oxidation can be obtained even when a material which contains oxygen, such as silicon oxide film, is used as the silicon-containing layer. This more certainly prevents the increase in resistance of the metal layer.
(7) According to the seventh aspect, at least a barrier metal layer is formed in the metal layer in contact with the silicon layer, which suppresses or prevents mutual reaction between the materials in the silicon layer and the metal layer.
(8) According to the eighth aspect, through the effect of any of the first to seventh aspects, this type of transistor can reduce the power dissipation and operate at higher speed, as compared with this type of transistor having a silicide gate (which corresponds to the conventional conductive layer) composed of a silicon layer and a silicide layer. Also the transistor can provide improved short-channel characteristic.
(9) According to the ninth aspect, the protective layer is formed on the side wall of the metal layer in the step (c). This prevents the metal layer from being oxidized in the following process steps, e.g. in treatments performed in an oxidation atmosphere. Further, even if a thermal treatment is performed after a material which contains oxygen is provided, the metal layer is not oxidized by the oxygen. Moreover, the metal layer is kept away from chemicals in various cleaning steps performed after the protective layer is formed, so that the metal layer will not be dissolved or deteriorated (particularly, not made insulating).
Particularly, since the step (d) of removing given part of the first silicon layer is carried out after the step (c) of forming the protective layer, by using anisotropic etching in the step (d), for example, the protective layer does not overhang relative to the remaining silicon layer. Thus the side wall of the protective layer and the side wall of the remaining silicon layer (the layer formed of the remaining silicon layer) can be formed in smooth shape. Accordingly, voids are not formed even when another layer (for example, side wall spacer in an MIS transistor) is formed on the side walls of the protective layer and the remaining silicon layer. This prevents the problem that oxygen and chemicals used in cleaning treatments enter through breaks of the film and pinholes formed due to such voids to oxidize or dissolve or deteriorate the metal layer.
As a result, it is possible to protect the metal layer from oxidation or/and dissolution or deterioration, and the increase in resistance of the metal layer can be certainly prevented in the semiconductor device. This also allows a wider range of choice of chemicals, thus providing the effect of more effectively performing cleaning.
(10) According to the tenth aspect, the silicide layer (protective layer) can be formed in a self-aligned manner and the protective layer can thus be formed easily and reliably on the side wall of the metal layer.
(11) According to the eleventh aspect, the size of the metal layer can be isotropically reduced by isotropic etching as compared with that formed by the semiconductor device manufacturing method of the ninth or tenth aspect. Accordingly, when the conductive layer including the metal layer and the remaining silicon layer is applied to the gate electrode of an MIS transistor, for example, the gate length can be adjusted and controlled. This enables larger current driving capability and further size reduction and higher degree of integration.
(12) According to the twelfth aspect, the metal layer is not oxidized because of the composition of the dielectric layer in and after the step (c), since the protective layer is made of a dielectric not containing oxygen. Also in treatments performed later in oxidation atmosphere, this prevents oxygen from entering the metal layer, thus preventing oxidation of the metal layer. As a result, it is possible to manufacture a semiconductor device in which the increase in the resistance of the metal layer due to the oxidation can certainly be prevented.
(13) According to the thirteenth aspect, damages given to the silicon layer in the step (d) can be reduced or removed. The effect of the ninth aspect is exerted also in the step (g) and the metal layer is not oxidized.
(14) According to the fourteenth aspect, keeping the silicon oxide film out of contact with the metal layer certainly prevents the silicon oxide film from oxidizing the metal layer. As a result, it is possible to more certainly prevent the increase in resistance of the metal layer, so as to provide a semiconductor device which is free from the increase in resistance of the metal layer due to oxidation.
(15) According to the fifteenth aspect, a barrier metal layer is formed in the metal layer in contact with the silicon layer, which suppresses or prevents mutual reaction between materials of the metal layer and the silicon layer in the manufacturing process.
(16) According to the sixteenth aspect, using the structure including the metal layer and the remaining silicon layer as a conductive layer provides the effect of any of the ninth to fifteenth aspects, thus providing a semiconductor device with reduced power dissipation and increased operation speed, as compared with the conventional conductive layer including a silicide layer and a silicon layer as the main materials.
The present invention has been made to solve the problems above, and an object of the present invention is to provide a semiconductor device having an electrode of the polymetal structure which can solve the above problems (1) to (5) all at once and a method of manufacturing the semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.